K50P121M100SF2V2 Datasheet, PDF (77/79 Pages) Freescale Semiconductor, Inc – K50 Sub-Family

121 Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
MAP
BGA
C4 PTC17
DISABLED
PTC17
UART3_TX
FB_CS4_b/
FB_TSIZ0/
FB_BE31_24_b
B4 PTC18
DISABLED
PTC18
UART3_RTS_b
FB_TBST_b/
FB_CS2_b/
FB_BE15_8_b
A4 PTC19
DISABLED
PTC19
UART3_CTS_b
FB_CS3_b/ FB_TA_b
FB_BE7_0_b
D4 PTD0/
LLWU_P12
DISABLED
PTD0/
LLWU_P12
SPI0_PCS0 UART2_RTS_b
FB_ALE/
FB_CS1_b/
FB_TS_b
D3 PTD1
ADC0_SE5b ADC0_SE5b PTD1
SPI0_SCK UART2_CTS_b
FB_CS0_b
C3 PTD2/
LLWU_P13
DISABLED
PTD2/
LLWU_P13
SPI0_SOUT UART2_RX
FB_AD4
B3 PTD3
DISABLED
PTD3
SPI0_SIN UART2_TX
FB_AD3
A3 PTD4/
LLWU_P14
DISABLED
PTD4/
LLWU_P14
SPI0_PCS1 UART0_RTS_b FTM0_CH4
FB_AD2
EWM_IN
A2 PTD5
ADC0_SE6b ADC0_SE6b PTD5
SPI0_PCS2
UART0_CTS_ FTM0_CH5
b/
UART0_COL_b
FB_AD1
EWM_OUT_b
B2 PTD6/
LLWU_P15
ADC0_SE7b ADC0_SE7b PTD6/
LLWU_P15
SPI0_PCS3 UART0_RX
FTM0_CH6
FB_AD0
FTM0_FLT0
A1 PTD7
DISABLED
PTD7
CMT_IRO UART0_TX FTM0_CH7
FTM0_FLT1
A10 PTD8
DISABLED
PTD8
I2C0_SCL UART5_RX
FB_A16
A9 PTD9
DISABLED
PTD9
I2C0_SDA UART5_TX
FB_A17
B1 PTD10
DISABLED
PTD10
UART5_RTS_b
FB_A18
C2 PTD11
DISABLED
PTD11
SPI2_PCS0 UART5_CTS_b SDHC0_CLKIN
FB_A19
C1 PTD12
DISABLED
PTD12
SPI2_SCK
SDHC0_D4
FB_A20
D2 PTD13
DISABLED
PTD13
SPI2_SOUT
SDHC0_D5
FB_A21
D1 PTD14
DISABLED
PTD14
SPI2_SIN
SDHC0_D6
FB_A22
E1 PTD15
DISABLED
PTD15
SPI2_PCS1
SDHC0_D7
FB_A23
A11 NC
NC
NC
B11 NC
NC
NC
C11 NC
NC
NC
Pinout
EzPort
8.2 K50 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
K50 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
Preliminary
77
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