K50P121M100SF2V2 Datasheet, PDF (75/79 Pages) Freescale Semiconductor, Inc – K50 Sub-Family

121 Pin Name
MAP
BGA
J6 PTA0
H8 PTA1
J7 PTA2
H9 PTA3
J8 PTA4/
LLWU_P3
K7 PTA5
E5 VDD
G3 VSS
J9 PTA10
Default
ALT0
JTAG_TCLK/
SWD_CLK/
EZP_CLK
JTAG_TDI/
EZP_DI
JTAG_TDO/
TRACE_SWO/
EZP_DO
JTAG_TMS/
SWD_DIO
NMI_b/
EZP_CS_b
DISABLED
VDD
VSS
DISABLED
TSI0_CH1
TSI0_CH2
TSI0_CH3
TSI0_CH4
TSI0_CH5
VDD
VSS
ALT1
PTA0
PTA1
PTA2
PTA3
PTA4/
LLWU_P3
PTA5
PTA10
K8 PTA12
CMP2_IN0 CMP2_IN0 PTA12
L8 PTA13/
LLWU_P4
K9 PTA14
L9 PTA15
J10 PTA16
CMP2_IN1 CMP2_IN1
DISABLED
DISABLED
DISABLED
PTA13/
LLWU_P4
PTA14
PTA15
PTA16
H10 PTA17
L10 VDD
K10 VSS
L11 PTA18
K11 PTA19
J11 RESET_b
H11 PTA29
G11 PTB0/
LLWU_P5
G10 PTB1
G9 PTB2
G8 PTB3
ADC1_SE17
VDD
VSS
EXTAL0
XTAL0
RESET_b
DISABLED
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
ADC0_SE12/
TSI0_CH7
ADC0_SE13/
TSI0_CH8
ADC1_SE17
VDD
VSS
EXTAL0
XTAL0
RESET_b
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
ADC0_SE12/
TSI0_CH7
ADC0_SE13/
TSI0_CH8
PTA17
PTA18
PTA19
PTA29
PTB0/
LLWU_P5
PTB1
PTB2
PTB3
F11 PTB6
E11 PTB7
ADC1_SE12 ADC1_SE12 PTB6
ADC1_SE13 ADC1_SE13 PTB7
Pinout
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
UART0_CTS_ FTM0_CH5
b/
UART0_COL_b
UART0_RX FTM0_CH6
UART0_TX FTM0_CH7
UART0_RTS_b FTM0_CH0
FTM0_CH1
USB_CLKIN FTM0_CH2
JTAG_TCLK/ EZP_CLK
SWD_CLK
JTAG_TDI EZP_DI
JTAG_TDO/ EZP_DO
TRACE_SWO
JTAG_TMS/
SWD_DIO
NMI_b
EZP_CS_b
CMP2_OUT I2S0_TX_BCLK JTAG_TRST_b
FTM2_CH0
FTM1_CH0
FTM1_CH1
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART0_TX
UART0_RX
UART0_CTS_
b/
UART0_COL_b
UART0_RTS_b
FTM2_QD_ TRACE_D0
PHA
I2S0_TXD0
FTM1_QD_
PHA
I2S0_TX_FS FTM1_QD_
PHB
I2S0_RX_BCLK I2S0_TXD1
I2S0_RXD0
I2S0_RX_FS I2S0_RXD1
I2S0_MCLK
FTM0_FLT2
FTM1_FLT0
FTM_CLKIN0
FTM_CLKIN1
LPTMR0_ALT1
I2C0_SCL FTM1_CH0
I2C0_SDA FTM1_CH1
I2C0_SCL UART0_RTS_b
I2C0_SDA
UART0_CTS_
b/
UART0_COL_b
FB_A24
FTM1_QD_
PHA
FTM1_QD_
PHB
FTM0_FLT3
FTM0_FLT0
FB_AD23
FB_AD22
K50 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
Preliminary
75
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