K50P121M100SF2V2 Datasheet, PDF (73/79 Pages) Freescale Semiconductor, Inc – K50 Sub-Family

Pinout
8.1 K50 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
121 Pin Name
MAP
BGA
E4 PTE0
E3 PTE1/
LLWU_P0
E2 PTE2/
LLWU_P1
F4 PTE3
E7 VDD
F7 VSS
H7 PTE4/
LLWU_P2
G4 PTE5
F3 PTE6
Default
ADC1_SE4a
ADC1_SE5a
ADC1_SE6a
ADC1_SE7a
VDD
VSS
DISABLED
DISABLED
DISABLED
ALT0
ADC1_SE4a
ADC1_SE5a
ADC1_SE6a
ADC1_SE7a
VDD
VSS
ALT1
PTE0
PTE1/
LLWU_P0
PTE2/
LLWU_P1
PTE3
PTE4/
LLWU_P2
PTE5
PTE6
ALT2
ALT3
ALT4
SPI1_PCS1
SPI1_SOUT
UART1_TX
UART1_RX
SDHC0_D1
SDHC0_D0
SPI1_SCK UART1_CTS_b SDHC0_DCLK
SPI1_SIN UART1_RTS_b SDHC0_CMD
SPI1_PCS0 UART3_TX SDHC0_D3
SPI1_PCS2
SPI1_PCS3
UART3_RX SDHC0_D2
UART3_CTS_b I2S0_MCLK
E6 VDD
G7 VSS
L6 VSS
F1 USB0_DP
F2 USB0_DM
G1 VOUT33
G2 VREGIN
H1 ADC0_DP1/
OP0_DP0
H2 ADC0_DM1/
OP0_DM0
J1 ADC1_DP1/
OP1_DP0/
OP1_DM1
J2 ADC1_DM1/
OP1_DM0
K1 PGA0_DP/
ADC0_DP0/
ADC1_DP3
K2 PGA0_DM/
ADC0_DM0/
ADC1_DM3
L1 PGA1_DP/
ADC1_DP0/
ADC0_DP3
VDD
VSS
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1/
OP0_DP0
ADC0_DM1/
OP0_DM0
ADC1_DP1/
OP1_DP0/
OP1_DM1
ADC1_DM1/
OP1_DM0
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
VDD
VSS
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1/
OP0_DP0
ADC0_DM1/
OP0_DM0
ADC1_DP1/
OP1_DP0/
OP1_DM1
ADC1_DM1/
OP1_DM0
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
ALT5
ALT6
ALT7
EzPort
I2C1_SDA
I2C1_SCL
RTC_CLKOUT
SPI1_SIN
SPI1_SOUT
USB_SOF_
OUT
K50 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
Preliminary
73
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