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K50P121M100SF2V2 Datasheet, PDF (47/79 Pages) Freescale Semiconductor, Inc – K50 Sub-Family | |||
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Peripheral operating requirements and behaviors
Table 30. 16-bit ADC with PGA characteristics (continued)
Symbol Description
G
Gain4
Conditions
⢠PGAG=0
⢠PGAG=1
⢠PGAG=2
⢠PGAG=3
⢠PGAG=4
⢠PGAG=5
⢠PGAG=6
Min.
Typ.1
Max.
Unit
Notes
0.95
1
1.05
1.9
2
2.1
RAS < 100Ω
3.8
4
4.2
7.6
8
8.4
15.2
16
16.6
30.0
31.6
33.2
58.8
63.3
67.8
BW
PSRR
Input signal
bandwidth
Power supply
rejection ratio
⢠16-bit modes
⢠< 16-bit modes
Gain=1
CMRR Common mode
rejection ratio
⢠Gain=1
⢠Gain=64
VOFS
TGSW
dG/dT
Input offset
voltage
Gain switching
settling time
Gain drift over full
temperature range
⢠Gain=1
⢠Gain=64
dG/dVDDA Gain drift over
supply voltage
⢠Gain=1
⢠Gain=64
EIL
Input leakage
error
All modes
â
â
4
â
â
40
â
-84
â
â
-84
â
â
-85
â
â
0.2
â
â
â
10
â
6
10
â
31
42
â
0.07
0.21
â
0.14
0.31
IIn à RAS
VPP,DIFF
Maximum
differential input
signal swing
SNR
Signal-to-noise
ratio
⢠Gain=1
⢠Gain=64
where VX = VREFPGA Ã 0.583
80
90
â
52
66
â
Table continues on the next page...
kHz
kHz
dB
VDDA= 3V
±100mV,
fVDDA= 50Hz,
60Hz
dB
VCM=
dB
500mVpp,
fVCM= 50Hz,
100Hz
mV Output offset =
VOFS*(Gain+1)
µs
5
ppm/°C
ppm/°C
%/V
%/V
mV
V
VDDA from 1.71
to 3.6V
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
6
dB
16-bit
dB
differential
mode,
Average=32
K50 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
Preliminary
47
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