MCIMX53XA Datasheet, PDF (76/180 Pages) Freescale Semiconductor, Inc – i.MX53xA Automotive and Infotainment Applications Processors

Electrical Characteristics
.
M7
FEC_TX_CLK (input)
FEC_TXD[3:0] (outputs)
FEC_TX_EN
FEC_TX_ER
M5
M8
M6
Figure 37. MII Transmit Signal Timing Diagram
4.7.5.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)
Table 50 lists MII asynchronous inputs signal timing information. Figure 38 shows MII asynchronous
input timings listed in Table 50.
Table 50. MII Async Inputs Signal Timing
Num
Characteristic ¹
M9²
FEC_CRS to FEC_COL minimum pulse width
1 _{Test conditions: 25pF on each output signal.}
2 _{FEC_COL has the same timing in 10 Mbit 7-wire interface mode.}
Min
Max
1.5
—
Unit
FEC_TX_CLK period
.
FEC_CRS, FEC_COL
M9
Figure 38. MII Async Inputs Timing Diagram
4.7.5.4 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)
Table 51 lists MII serial management channel timings. Figure 39 shows MII serial management channel
timings listed in Table 51. The MDC frequency should be equal to or less than 2.5 MHz to be compliant
with the IEEE 802.3 MII specification. However, the FEC can function correctly with a maximum MDC
frequency of 15 MHz.
Table 51. MII Transmit Signal Timing
ID
Characteristics¹
Min Max
Unit
M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay)
0—
ns
M11 FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay)
—5
ns
M12 FEC_MDIO (input) to FEC_MDC rising edge setup
18 —
ns
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
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