MCIMX53XA Datasheet, PDF (29/180 Pages) Freescale Semiconductor, Inc – i.MX53xA Automotive and Infotainment Applications Processors

Electrical Characteristics
Table 10. GPIO I/O DC Electrical Characteristics (continued)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Low-level output current
(1.65-3.1V OVDD)
High-Level DC input voltage^{1, 2}
Low-Level DC input voltage^{1, 2}
Iol
Vout = 0.2×OVDD
Low drive
Medium drive
High drive
Max drive
VIH
—
VIL
—
2.1
4.2
—
—
mA
6.3
8.4
0.7 × OVDD —
OVDD
V
0
— 0.3 × OVDD
V
Input Hysteresis
Schmitt trigger VT+^{2, 3}
Schmitt trigger VT–^{2, 3}
VHYS
VT+
VT–
OVDD = 1.875 V
OVDD = 2.775 V
—
—
0.25
0.34
—
V
0.45
0.5 × OVDD —
—
V
—
— 0.5 × OVDD
V
Input current (no pull-up/down)
IIN
VI = 0 V
VI = OVDD
1.7
—
250
120
nA
Input current (22 kΩ Pull-up)
IIN
VI = 0 V
VI = OVDD
—
—
161
0.12
μA
Input current (47 kΩ Pull-up)
IIN
VI = 0 V
VI = OVDD
—
—
76
0.12
μA
Input current (100 kΩ Pull-up)
IIN
VI = 0 V
V I= OVDD
—
—
36
0.12
μA
Input current (100 kΩ Pull-down)
IIN
VI = 0 V
VI = OVDD
—
—
0.25
36
μA
Keeper Circuit Resistance
—
125⁴
—
kΩ
1 _{Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,}
and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be
controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other
methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
2 _{To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC}
level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.
3 _{Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.}
4 _{Use an off-chip pull resistor of less than 60kΩ to override this keeper.}
4.3.2 LPDDR2 I/O DC Parameters
The LPDDR2 I/O pads support DDR2/LVDDR2, LPDDR2, and DDR3 operational modes.
4.3.2.1 DDR2 Mode I/O DC Parameters
The DDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The
parameters in Table 11 are guaranteed per the operating ranges in Table 6, unless otherwise noted.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
Freescale Semiconductor
29