56F8014 Datasheet, PDF (75/124 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Register Descriptions
6.3.10 I/O Short Address Location Register (SIM_IOSAHI and
SIM_IOSALO)
The I/O Short Address Location registers are used to specify the memory referenced via the I/O short
address mode. The I/O short address mode allows the instruction to specify the lower six bits of address;
the upper address bits are not directly controllable. This register set allows limited control of the full
address, as shown in Figure 6-12.
“Hard Coded” Address Portion ^{Instruction Portion}
6 Bits from I/O Short Address Mode Instruction
16 Bits from SIM_IOSALO Register
2 bits from SIM_IOSAHI Register
Full 24-Bit for Short I/O Address
Figure 6-12 I/O Short Address Determination
With this register set, an interrupt driver can set the SIM_IOSALO register pair to point to its peripheral
registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register
to its previous contents prior to returning from interrupt.
Note:
The default value of this register set points to the EOnCE registers.
Note:
The pipeline delay between setting this register set and using short I/O addressing with the new value
is five instruction cycles.
Base + $D 15 14 13 12 11 10 9
8
7
6
5
4
3
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
2
10
0
ISAL[23:22]
0
1
1
Figure 6-13 I/O Short Address Location High Register (SIM_IOSAHI)
6.3.10.1 Reserved—Bits 15—2
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
75
Preliminary