56F8014 Datasheet, PDF (110/124 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Table 10-19 ADC Parameters¹ (Continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Offset Voltage Internal Ref
Gain Error (transfer gain)
Offset Voltage External Ref
Signal-to-noise ratio
Total Harmonic Distortion
V_OFFSET
E_GAIN
V_OFFSET
SNR
THD
—
.99
—
TBD
TBD
+/- 8
1
+/- 3
62 to 65.7
63 to 68
+/- 15
mV
1.01
—
TBD
mV
dB
dB
Spurious Free Dynamic Range
SFDR
TBD
67 to 70.3
dB
Signal-to-noise plus distortion
SINAD
TBD
61 to 63.9
dB
Effective Number Of Bits
ENOB
9.1
9.6 to 10.4
Bits
1. All measurements were made at V_DD = 3.3V, V_REFH = 3.3V, and V_REFL = ground
2. INL measured from V_IN = V_REFL to V_IN = V_REFH
3. LSB = Least Significant Bit
4. INL measure from V_IN = 0.1 V_REFH to V_IN = 0.9V_REFH
5. Includes power-up of ADC and V_REF
6. ADC clock cycles
7. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance
of the ADC.
10.15 Equivalent Circuit for ADC Inputs
Figure 10-17 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed
at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and
hold circuit moves to (V_REFH-V_REFL)/2, while the other charges to the analog input voltage. When the
switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended
analog input is switched to a differential voltage centered about (V_REFH-V_REFL)/2. The switches switch
on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there
are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into
the S/H output voltage, as S1 provides isolation during the charge-sharing phase.
One aspect of this circuit is that there is an on-going input current, which is a function of the analog input
voltage, V_REF and the ADC clock frequency.
56F8014 Technical Data, Rev. 3
110
Freescale Semiconductor
Preliminary