56F8014 Datasheet, PDF (121/124 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Electrical Design Considerations
Module
Register Name
Peripheral Reference Manual
New Acronym
Legacy
Acronym
Data Sheet
New Acronym Legacy Acronym
Processor
Expert
Acronym
Memory Address
Start End
FM Clock Divider Register
Configuration Register
Security High Half Register
Security Low Half Register
Protection Register
User Status Register
Command Register
Address Register
Data Buffer Register
Optional Data 1 Register
Test Array Signature Register
CLKDIV
CNFG
SECHI
SECLO
PROT
USTAT
CMD
ADDR
DATA
OPT1
TSTSIG
FMCLKD
FMCR
FMSECH
FMSECL
FMPROT
FMUSTAT
FMCMD
FMADDR
FMDATA
FMOPT1
FMTST_SIG
FM_CLKDIV
FM_CNFG
FM_SECHI
FM_SECLO
FM_PROT
FM_USTAT
FM_CMD
FM_ADDR
FM_DATA
FM_OPT1
FM_TSTSIG
FMCLKD
FMCR
FMSECH
FMSECL
FMPROT
FMUSTAT
FMCMD
FMADDR
FMDATA
FMOPT1
FMTST_SIG
FMCLKD
FMCR
FMSECH
FMSECL
FMPROT
FMUSTAT
FMCMD
FMOPT1
0xF400
0xF401
0xF403
0xF404
0xF410
0xF413
0xF414
0xF416
0xF418
0xF41B
0xF41D
GPIO
Pull-Up Enable Register
Data Register
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Edge Polarity Register
Interrupt Pending Register
Interrupt Edge Sensitive Register
Push-Pull Output Mode Control Register
Raw Data Register
Drive Strength Control Register
PUPEN
DATA
DDIR
PEREN
IASSRT
IEN
IEPOL
IPEND
IEDGE
PPOUTM
RDATA
DRIVE
PUR
DR
DDR
PER
IAR
IENR
IPOLR
IPR
IESR
PPMODE
RAWDATA
DRIVE
x = A (n=0) B (n=1) C (n=2) D (n=3)
GPIOx_PUPEN
GPIOx_PUR
GPIO_x_PUR
0xF1n0
GPIOx_DATA
GPIOx_DR
GPIO_x_DR
0xF1n1
GPIOx_DDIR
GPIOx_DDR
GPIO_x_DDR
0xF1n2
GPIOx_PEREN
GPIOx_PER
GPIO_x_PER
0xF1n3
GPIOx_IASSRT
GPIOx_IAR
GPIO_x_IAR
0xF1n4
GPIOx_IEN
GPIOx_IENR
GPIO_x_IENR
0xF1n5
GPIOx_IEPOL GPIOx_IPOLR
GPIO_x_IPOLR
0xF1n6
GPIOx_IPEND
GPIOx_IPR
GPIO_x_IPR
0xF1n7
GPIOx_IEDGE
GPIOx_IESR
GPIO_x_IESR
0xF1n8
GPIOx_PPOUTM GPIOx_PPMODE GPIO_x_PPMODE
0xF1n9
GPIOx_RDATA GPIOx_RAWDATA GPIO_x_RAWDATA
0xF1nA
GPIOx_DRIVE GPIOx_DRIVE
GPIO_x_DRIVE
0xF1nB
PS Control Register
Status Register
CTRL
STAT
LVICONTROL
LVISTATUS
PS_CTRL
PS_STAT
LVICONTROL
LVISTATUS
LVICTRL
LVISR
0xF160
0xF161
PWM
Control Register
Fault Control Register
Fault Status/Acknowledge Regis.
Output Control Register
Counter Register
Counter Modulo Register
Value Register 0-5
Deadtime Register 0-1
Disable Mapping Register 1-2
Configure Register
Channel Control Register
Port Register
Internal Correction Control Regis.
Source Control Register
CTRL
FCTRL
FLTACK
OUT
CNTR
CMOD
VAL0-5
DTIM0-1
DMAP1-2
CNFG
CCTRL
PORT
ICCTRL
SCTRL
PMCTL
PMFCTL
PMFSA
PMOUT
PMCNT
MCM
PMVAL0-5
PMDEADTM0-1
PMDISMAP1-2
PMCFG
PMCCR
PMPORT
PMICCR
PMSRC
PWM_CTRL
PWM_FCTRL
PWM_FLTACK
PWM_OUT
PWM_CNTR
PWM_CMOD
PWM_VAL0-5
PWM_DTIM0-1
PWM_DMAP1-2
PWM_CNFG
PWM_CCTRL
PWM_PORT
PWM_ICCTRL
PWM_SCTRL
PWM_PMCTL
PWM_PMCTL
0xF040
PWM_PMFCTL
PWM_PMFCTL
0xF041
PWM_PMFSA
PWM_PMFSA
0xF042
PWM_PMOUT
PWM_PMOUT
0xF043
PWM_PMCNT
PWM_PMCNT
0xF044
PWM_MCM
PWM_PWMCM
0xF045
PWM_PMVAL0-5 PWM_PWMVAL0-5 0xF046 0xF04B
PWM_PMDEADTM PWM_PMDEADTM0- 0xF04C 0xF04D
0-1
1
PWM_PMDISMAP1- PWM_PMDISMAP1-2 0xF04E 0xF04F
2
PWM_PMCFG
PWM_PMCFG
0xF050
PWM_PMCCR
PWM_PMCCR
0xF051
PWM_PMPORT
PWM_PMPORT
0xF052
PWM_PMICCR
PWM_PMICCR
0xF053
PWM_PMSRC
PWM_PMSRC
0xF054
SCI Baud Rate Register
Control Register 1
Control Register 2
Status Register
Data Register
Module
Register Name
RATE
SCIBR
CTRL1
SCICR
CTRL2
SCICR2
STAT
SCISR
DATA
SCIDR
Peripheral Reference Manual
New Acronym
Legacy
Acronym
SCI_RATE
SCI_SCIBR
SCI_CTRL1
SCI_SCICR
SCI_CTRL2
SCI_SCICR2
SCI_STAT
SCI_SCISR
SCI_DATA
SCI_SCIDR
Data Sheet
New Acronym Legacy Acronym
SCI_SCIBR
SCI_SCICR
SCI_SCICR2
SCI_SCISR
SCI_SCIDR
Processor
Expert
Acronym
0xF0B0
0xF0B1
0xF0B2
0xF0B3
0xF0B4
Memory Address
Start End
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
121
Preliminary