|
MC9S12HZ256_08 Datasheet, PDF (73/692 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
|
◁ |
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
Table 2-16. FSTAT Field Descriptions
Field
Description
7
CBEIF
Command Buffer Empty Interrupt Flag â The CBEIF ï¬ag indicates that the address, data and command
buffers are empty so that a new command write sequence can be started. The CBEIF ï¬ag is cleared by writing
a 1 to CBEIF. Writing a 0 to the CBEIF ï¬ag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned
word to the Flash address space but before CBEIF is cleared will abort a command write sequence and cause
the ACCERR ï¬ag to be set. Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR
ï¬ag. The CBEIF ï¬ag is used together with the CBEIE bit in the FCNFG register to generate an interrupt request
(see Figure 2-29).
0 Buffers are full.
1 Buffers are ready to accept a new command.
6
CCIF
Command Complete Interrupt Flag â The CCIF ï¬ag indicates that there are no more commands pending. The
CCIF ï¬ag is cleared when CBEIF is clear and sets automatically upon completion of all active and pending
commands. The CCIF ï¬ag does not set when an active commands completes and a pending command is
fetched from the command buffer. Writing to the CCIF ï¬ag has no effect on CCIF. The CCIF ï¬ag is used together
with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 2-29).
0 Command in progress.
1 All commands are completed.
5
PVIOL
Protection Violation Flag â The PVIOL ï¬ag indicates an attempt was made to program or erase an address
in a protected area of the Flash block during a command write sequence. The PVIOL ï¬ag is cleared by writing a
1 to PVIOL. Writing a 0 to the PVIOL ï¬ag has no effect on PVIOL. While PVIOL is set, it is not possible to launch
a command or start a command write sequence.
0 No failure.
1 A protection violation has occurred.
4
ACCERR
Access Error Flag â The ACCERR ï¬ag indicates an illegal access to the Flash array caused by either a
violation of the command write sequence, issuing an illegal command (illegal combination of the CMDBx bits in
the FCMD register), launching the sector erase abort command terminating a sector erase operation early or the
execution of a CPU STOP instruction while a command is executing (CCIF = 0). The ACCERR ï¬ag is cleared by
writing a 1 to ACCERR. Writing a 0 to the ACCERR ï¬ag has no effect on ACCERR. While ACCERR is set in any
of the banked FTSAT registers, it is not possible to launch a command or start a command write sequence in any
of the Flash blocks. If ACCERR is set by an erase verify operation or a data compress operation, any buffered
command will not launch.
0 No access error detected.
1 Access error has occurred.
2
BLANK
Erase Verify Operation Status Flag â When the CCIF ï¬ag is set after completion of an erase verify command,
the BLANK ï¬ag indicates the result of the erase verify operation. The BLANK ï¬ag is cleared by the Flash module
when CBEIF is cleared as part of a new valid command write sequence. Writing to the BLANK ï¬ag has no effect
on BLANK.
0 Flash block veriï¬ed as not erased.
1 Flash block veriï¬ed as erased.
1
FAIL
Flag Indicating a Failed Flash Operation â The FAIL ï¬ag will set if the erase verify operation fails (selected
Flash block veriï¬ed as not erased). The FAIL ï¬ag is cleared by writing a 1 to FAIL. Writing a 0 to the FAIL ï¬ag
has no effect on FAIL.
0 Flash operation completed without error.
1 Flash operation failed.
2.3.2.8 Flash Command Register (FCMD)
The banked FCMD register is the Flash command register.
MC9S12HZ256 Data Sheet, Rev. 2.05
Freescale Semiconductor
73
|
▷ |