MC9S12HZ256_08 Datasheet, PDF (132/692 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.2.4 Port L Reduced Drive Register (RDRL)
R
W
Reset
7
RDRL7
0
6
RDRL6
5
RDRL5
4
RDRL4
3
RDRL3
2
RDRL2
0
0
0
0
0
Figure 4-13. Port L Reduced Drive Register (RDRL)
1
RDRL1
0
0
RDRL0
0
Read: Anytime. Write: Anytime.
This register configures the drive strength of configured output pins as either full or reduced. If a pin is
configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 4-10. RDRL Field Descriptions
Field
Description
7:0
Reduced Drive Port L
RDRL[7:0] 0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.
4.3.2.5 Port L Pull Device Enable Register (PERL)
7
R
PERL7
W
6
PERL6
5
PERL5
4
PERL4
3
PERL3
2
PERL2
1
PERL1
0
PERL0
Reset
1
1
1
1
1
1
1
1
Figure 4-14. Port L Pull Device Enable Register (PERL)
Read:Anytime. Write:Anytime.
This register configures whether a pull-up or a pull-down device is activated on configured input pins. If
a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
Table 4-11. PERL Field Descriptions
Field
7:0
Pull Device Enable Port L
PERL[7:0] 0 Pull-up or pull-down device is disabled.
1 Pull-up or pull-down device is enabled.
Description
MC9S12HZ256 Data Sheet, Rev. 2.05
132
Freescale Semiconductor