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MC9S12HZ256_08 Datasheet, PDF (649/692 Pages) Freescale Semiconductor, Inc – Microcontrollers
Appendix A Electrical Characteristics
SS1
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
1
2
4
4
5
6
MSB IN2
12
11
BIT 6 . . . 1
9
(OUMTPOUSTI)PORT DATA
10
MASTER MSB OUT2 BIT 6 . . . 1
11
3
12
LSB IN
MASTER LSB OUT PORT DATA
1. If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-7. SPI Master Timing (CPHA =1)
Table A-19. SPI Master Mode Timing Characteristics1
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num C
Rating
Symbol
Min
Typ
Max
Unit
1 P Operating Frequency
fop
DC
1/4
fbus
1 P SCK Period tsck = 1./fop
tsck
4
2048
tbus
2 D Enable Lead Time
tlead
1/2
—
tsck
3 D Enable Lag Time
tlag
1/2
tsck
4 D Clock (SCK) High or Low Time
twsck
tbus − 30
1024 tbus
ns
5 D Data Setup Time (Inputs)
tsu
25
ns
6 D Data Hold Time (Inputs)
thi
0
ns
9 D Data Valid (after SCK Edge)
tv
25
ns
10 D Data Hold Time (Outputs)
tho
0
ns
11 D Rise Time Inputs and Outputs
tr
25
ns
12 D Fall Time Inputs and Outputs
tf
25
ns
1 The numbers 7, 8 in the column labeled “Num” are missing. This has been done on purpose to be consistent between the
Master and the Slave timing shown in Table A-20.
MC9S12HZ256 Data Sheet, Rev. 2.05
Freescale Semiconductor
649