MC9S12HZ256_08 Datasheet, PDF (165/692 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4 Port Integration Module (PIM9HZ256V2)
t_pulse
Figure 4-58. Pulse Illustration
A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4
consecutive samples of an active level directly or indirectly
The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock
is generated by a single RC oscillator in the port integration module. To maximize current saving the RC
oscillator runs only if the following condition is true on any pin:
Sample count <= 4 and port interrupt enabled (PIE=1) and port interrupt flag not set (PIF=0).
4.6.2
Interrupt Sources
Table 4-43. Port Integration Module Interrupt Sources
Interrupt
Source
Port AD
Interrupt
Flag
PIFAD[7:0]
Local
Enable
PIEAD[7:0]
Global (CCR)
Mask
I Bit
NOTE
Vector addresses and their relative interrupt priority are determined at the
MCU level.
4.6.3 Operation in Stop Mode
All clocks are stopped in STOP mode. The port integration module has asynchronous paths on port AD to
generate wake-up interrupts from stop mode. For other sources of external interrupts refer to the respective
block description chapters.
MC9S12HZ256 Data Sheet, Rev. 2.05
Freescale Semiconductor
165