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MC9S12HZ256_08 Datasheet, PDF (197/692 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Chapter 5 Clocks and Reset Generator (CRGV4)
Table 5-12. Outcome of Clock Loss in Pseudo-Stop Mode
CME SCME SCMIE
CRG Actions
0
X
1
0
1
1
X Clock failure -->
No action, clock loss not detected.
X Clock failure -->
CRG performs Clock Monitor Reset immediately
0 Clock Monitor failure -->
Scenario 1: OSCCLK recovers prior to exiting Pseudo-Stop Mode.
â MCU remains in Pseudo-Stop Mode,
â VREG enabled,
â PLL enabled,
â SCM activated,
â Start Clock Quality Check,
â Set SCMIF interrupt ï¬ag.
Some time later OSCCLK recovers.
â CM no longer indicates a failure,
â 4096 OSCCLK cycles later Clock Quality Check indicates clock o.k.,
â SCM deactivated,
â PLL disabled,
â VREG disabled.
â MCU remains in Pseudo-Stop Mode.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
â Exit Pseudo-Stop Mode using OSCCLK as system clock (SYSCLK),
â Continue normal operation.
or an External Reset is applied.
â Exit Pseudo-Stop Mode using OSCCLK as system clock,
â Start reset sequence.
Scenario 2: OSCCLK does not recover prior to exiting Pseudo-Stop Mode.
â MCU remains in Pseudo-Stop Mode,
â VREG enabled,
â PLL enabled,
â SCM activated,
â Start Clock Quality Check,
â Set SCMIF interrupt ï¬ag,
â Keep performing Clock Quality Checks (could continue inï¬nitely)
while in Pseudo-Stop Mode.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
â Exit Pseudo-Stop Mode in SCM using PLL clock (fSCM) as system clock
â Continue to perform additional Clock Quality Checks until OSCCLK
is o.k. again.
or an External RESET is applied.
â Exit Pseudo-Stop Mode in SCM using PLL clock (fSCM) as system clock
â Start reset sequence,
â Continue to perform additional Clock Quality Checks until OSCCLK
is o.k.again.
MC9S12HZ256 Data Sheet, Rev. 2.05
Freescale Semiconductor
197
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