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S9S12GN48F0CLH Datasheet, PDF (713/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet | |||
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Serial Peripheral Interface (S12SPIV5)
Table 21-7. SPISR Field Descriptions
Field
5
SPTEF
4
MODF
Description
SPI Transmit Empty Interrupt Flag â If set, this bit indicates that the transmit data register is empty. For
information about clearing this bit and placing data into the transmit data register, please refer to Table 21-9.
0 SPI data register not empty.
1 SPI data register empty.
Mode Fault Flag â This bit is set if the SS input becomes low while the SPI is conï¬gured as a master and mode
fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
Section 21.3.2.2, âSPI Control Register 2 (SPICR2)â. The ï¬ag is cleared automatically by a read of the SPI status
register (with MODF set) followed by a write to the SPI control register 1.
0 Mode fault has not occurred.
1 Mode fault has occurred.
Table 21-8. SPIF Interrupt Flag Clearing Sequence
XFRW Bit
SPIF Interrupt Flag Clearing Sequence
0
Read SPISR with SPIF == 1 then
Read SPIDRL
1
Read SPISR with SPIF == 1
Byte Read SPIDRL 1
or
then Byte Read SPIDRH 2 Byte Read SPIDRL
or
Word Read (SPIDRH:SPIDRL)
1 Data in SPIDRH is lost in this case.
2 SPIDRH can be read repeatedly without any effect on SPIF. SPIF Flag is cleared only by the read
of SPIDRL after reading SPISR with SPIF == 1.
Table 21-9. SPTEF Interrupt Flag Clearing Sequence
XFRW Bit
SPTEF Interrupt Flag Clearing Sequence
0
Read SPISR with SPTEF == 1 then
Write to SPIDRL 1
1 Read SPISR with SPTEF == 1
Byte Write to SPIDRL 12
or
then Byte Write to SPIDRH 13 Byte Write to SPIDRL 1
or
Word Write to (SPIDRH:SPIDRL) 1
1 Any write to SPIDRH or SPIDRL with SPTEF == 0 is effectively ignored.
2 Data in SPIDRH is undeï¬ned in this case.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
715
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