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S9S12GN48F0CLH Datasheet, PDF (1238/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet | |||
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Electrical Characteristics
A.12 Electrical Speciï¬cation for Voltage Regulator
Table A-43. Voltage Regulator Characteristics (Junction Temperature From â40°C To +150°C)
Num C
Characteristic
Symbol
Min
Typical
Max
Unit
1
P Input Voltages
VVDDR,A
3.13
2
P
VDDA Low Voltage Interrupt Assert Level 1
VDDA Low Voltage Interrupt Deassert Level
VLVIA
VLVID
4.04
4.19
3
P
VDDX Low Voltage Reset Deassert 2 3 4
VLVRXD
â
4
P
VDDX Low Voltage Reset Assert 2 3 4
VLVRXA
2.95
5
T
CPMU ACLK frequency
(CPMUACLKTR[5:0] = %000000)
fACLK
â
6
C
Trimmed ACLK internal clock5 âf / fnominal
dfACLK
- 5%
7
The first period after enabling the counter
D by APIFE might be reduced by ACLK start
tsdel
â
up delay
8
D
The first period after enabling the COP
might be reduced by ACLK start up delay
tsdel
â
9
Output Voltage Flash
P
Full Performance Mode
VDDF
2.6
Reduced Power Mode (MCU STOP mode)
1.1
â
4.23
4.38
3.05
3.02
10
â
â
â
2.82
1.6
5.5
V
4.40
V
4.49
V
3.13
V
â
V
â
KHz
+ 5%
â
100
us
100
us
2.9
V
1.98
V
10
VDDF Voltage Distribution
C
over input voltage VDDA6
4.5V ⤠VDDA ⤠5.5V, TA = 27oC
compared to VDDA = 5.0V
âVDDF
-5
0
5
mV
11
VDDF Voltage Distribution
over ambient temperature TA
C
VDDA = 5V, -40°C ⤠TA ⤠125°C
compared to VDDF production test value
âVDDF
-20
-
+20
mV
(see A.16, âADC Conversion Result
Referenceâ)
1 Monitors VDDA, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to low supply
voltage.
2 Device functionality is guaranteed on power down to the LVR assert level
3 Monitors VDDX, active only in Full Performance Mode. MCU is monitored by the POR in RPM (see Figure A-6)
4 VLVRXA < VLVRXD. The hysteresis is unspeciï¬ed and untested.
5 The ACLK Trimming CPMUACLKTR[5:0] bits must be set so that fACLK=10KHz.
6 VDDR ⥠3.13V
1240
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
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