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S9S12GN48F0CLH Datasheet, PDF (371/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet | |||
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S12 Clock, Reset and Power Management Unit (S12CPMU)
10.3.2 Register Descriptions
This section describes all the S12CPMU registers and their individual bits.
Address order is as listed in Figure 10-3.
10.3.2.1 S12CPMU Synthesizer Register (CPMUSYNR)
The CPMUSYNR register controls the multiplication factor of the PLL and selects the VCO frequency
range.
0x0034
7
6
5
4
3
2
1
0
R
VCOFRQ[1:0]
W
SYNDIV[5:0]
Reset
0
1
0
1
1
0
0
0
Figure 10-4. S12CPMU Synthesizer Register (CPMUSYNR)
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has
no effect.
NOTE
Writing to this register clears the LOCK and UPOSC status bits.
If PLL has locked (LOCK=1)
fVCO = 2 Ã fREF Ã (SYNDIV + 1)
NOTE
fVCO must be within the speciï¬ed VCO frequency lock range. Bus
frequency fbus must not exceed the speciï¬ed maximum.
The VCOFRQ[1:0] bits are used to conï¬gure the VCO gain for optimal stability and lock time. For correct
PLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK
frequency as shown in Table 10-1. Setting the VCOFRQ[1:0] bits incorrectly can result in a non functional
PLL (no locking and/or insufï¬cient stability).
Table 10-1. VCO Clock Frequency Selection
VCOCLK Frequency Ranges
32MHz <= fVCO<= 48MHz
48MHz < fVCO<= 50MHz
Reserved
Reserved
VCOFRQ[1:0]
00
01
10
11
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
373
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