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S9S12GN48F0CLH Datasheet, PDF (1095/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet | |||
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192 KByte Flash Module (S12FTMRG192K2V1)
Offset Module Base + 0x0000
7
6
5
4
3
2
1
0
R FDIVLD
W
FDIVLCK
FDIV[5:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 30-5. Flash Clock Divider Register (FCLKDIV)
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the
writability of the FDIV ï¬eld in normal mode. In special mode, bits 6-0 are writable any number of times
but bit 7 remains unwritable.
CAUTION
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0).
Table 30-7. FCLKDIV Field Descriptions
Field
Description
7
FDIVLD
6
FDIVLCK
5â0
FDIV[5:0]
Clock Divider Loaded
0 FCLKDIV register has not been written since the last reset
1 FCLKDIV register has been written since the last reset
Clock Divider Locked
0 FDIV ï¬eld is open for writing
1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and
restore writability to the FDIV ï¬eld in normal mode.
Clock Divider Bits â FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events
during Flash program and erase algorithms. Table 30-8 shows recommended values for FDIV[5:0] based on the
BUSCLK frequency. Please refer to Section 30.4.4, âFlash Command Operations,â for more information.
Freescale Semiconductor
MC9S12G Family Reference Manual, Rev.1.23
1097
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