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S9S12GN48F0CLH Datasheet, PDF (1049/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet | |||
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128 KByte Flash Module (S12FTMRG128K1V1)
Table 29-15. FSTAT Field Descriptions (continued)
Field
Description
3
MGBUSY
2
RSVD
Memory Controller Busy Flag â The MGBUSY ï¬ag reï¬ects the active state of the Memory Controller.
0 Memory Controller is idle
1 Memory Controller is busy executing a Flash command (CCIF = 0)
Reserved Bit â This bit is reserved and always reads 0.
1â0
Memory Controller Command Completion Status Flag â One or more MGSTAT ï¬ag bits are set if an error
MGSTAT[1:0] is detected during execution of a Flash command or during the Flash reset sequence. See Section 29.4.6,
âFlash Command Description,â and Section 29.6, âInitializationâ for details.
29.3.2.8 Flash Error Status Register (FERSTAT)
The FERSTAT register reï¬ects the error status of internal Flash operations.
Offset Module Base + 0x0007
7
R
0
W
Reset
0
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 29-12. Flash Error Status Register (FERSTAT)
1
DFDIF
0
0
SFDIF
0
All ï¬ags in the FERSTAT register are readable and only writable to clear the ï¬ag.
Table 29-16. FERSTAT Field Descriptions
Field
Description
1
DFDIF
Double Bit Fault Detect Interrupt Flag â The setting of the DFDIF ï¬ag indicates that a double bit fault was
detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation
returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The DFDIF
ï¬ag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.2
0 No double bit fault detected
1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command
running
0
SFDIF
Single Bit Fault Detect Interrupt Flag â With the IGNSF bit in the FCNFG register clear, the SFDIF ï¬ag
indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation
or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash
command operation.1 The SFDIF ï¬ag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on
SFDIF.
0 No single bit fault detected
1 Single bit fault detected and corrected or a Flash array read operation returning invalid data was attempted
while command running
1 The single bit fault and double bit fault ï¬ags are mutually exclusive for parity errors (an ECC fault occurrence can be either
single fault or double fault but never both). A simultaneous access collision (Flash array read operation returning invalid data
attempted while command running) is indicated when both SFDIF and DFDIF ï¬ags are high.
2 There is a one cycle delay in storing the ECC DFDIF and SFDIF fault ï¬ags in this register. At least one NOP is required after
a ï¬ash memory read before checking FERSTAT for the occurrence of ECC errors.
Freescale Semiconductor
MC9S12G Family Reference Manual, Rev.1.23
1051
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