K61P144M120SF3 Datasheet, PDF (70/82 Pages) Freescale Semiconductor, Inc – K61 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
Table 49. I2S/SAI master mode timing
Num.
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
Characteristic
Operating voltage
I2S_MCLK cycle time¹
I2S_MCLK pulse width high/low
I2S_TX_BCLK cycle time (output)¹
I2S_RX_BCLK cycle time (output)¹
I2S_TX_BCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid²
Min.
1.71
40
45%
80
160
45%
—
0
—
0
25
0
—
Max.
3.6
55%
—
—
55%
15
—
15
—
—
—
21
Unit
V
ns
MCLK period
ns
BCLK period
ns
ns
ns
ns
ns
ns
ns
1. This parameter is limited in VLPx modes.
2. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
S1
S2
S2
S3
S4
S4
S5
S9
S7
S9
S10
S7
S8
S6
S10
S8
Figure 33. I2S/SAI timing — master modes
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
70
Preliminary
Freescale Semiconductor, Inc.