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K61P144M120SF3 Datasheet, PDF (17/82 Pages) Freescale Semiconductor, Inc – K61 Sub-Family Data Sheet | |||
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5.2.4 Power mode transition operating behaviors
General
All specifications except tPOR, and VLLSxâRUN recovery times in the following table
assume this clock configuration:
⢠CPU and system clocks = FEI 100 MHz
⢠Bus clock = 50 MHz
⢠FlexBus clock = 50 MHz
⢠Flash clock = 25 MHz
Symbol
tPOR
Table 5. Power mode transition operating behaviors
Description
Min.
Max.
Unit
After a POR event, amount of time from the point VDD
â
300
μs
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
⢠VLLS1 â RUN
â
126
μs
Notes
1
⢠VLLS2 â RUN
â
82
μs
⢠VLLS3 â RUN
â
82
μs
⢠LLS â RUN
â
5.0
μs
⢠VLPS â RUN
â
TBD
μs
⢠STOP â RUN
â
TBD
μs
1. Normal boot (FTFE_FOPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Run mode current â all peripheral clocks
disabled, code executing from flash
⢠@ 1.8V
⢠@ 3.0V
Min.
â
â
â
Typ.
Max.
Unit
â
See note
mA
65
TBD
mA
65
TBD
mA
IDD_RUN
Run mode current â all peripheral clocks
enabled, code executing from flash
⢠@ 1.8V
⢠@ 3.0V
â
95
TBD
mA
â
95
TBD
mA
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
Notes
1
2
3
17
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