K61P144M120SF3 Datasheet, PDF (68/82 Pages) Freescale Semiconductor, Inc – K61 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 47. Slave mode DSPI timing (full voltage range) (continued)
Num
DS16
Description
DSPI_SS inactive to DSPI_SOUT not driven
Min.
Max.
Unit
—
19
ns
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
DS10
DS15
DS13
First data
DS14
First data
DS12
Data
Data
DS9
DS11
Last data
DS16
Last data
Figure 31. DSPI classic SPI timing — slave mode
6.8.9 _I²_{C switching specifications}
See General switching specifications.
6.8.10 UART switching specifications
See General switching specifications.
6.8.11 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 48. SDHC switching specifications
Num
Symbol
Description
Operating voltage
Card input clock
Min.
Max.
Unit
2.7
3.6
V
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
68
Preliminary
Freescale Semiconductor, Inc.