K61P144M120SF3 Datasheet, PDF (38/82 Pages) Freescale Semiconductor, Inc – K61 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 23. EzPort switching specifications (continued)
Num
EP8
EP9
Description
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
Min.
Max.
Unit
0
—
ns
—
12
ns
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
EP3
EP4
EP2
EP9
EP8
EP7
EP5
EP6
Figure 10. EzPort Timing Diagram
6.4.3 NFC specifications
The NAND flash controller (NFC) implements the interface to standard NAND flash
memory devices. This section describes the timing parameters of the NFC.
In the following table:
• T_H is the flash clock high time and
• T_L is flash clock low time,
which are defined as:
T _NFC = T _L + T _H =
T _{input clock}
SCALER
The SCALER value is derived from the fractional divider specified in the SIM's
CLKDIV4 register:
SCALER ⁼
SIM_CLKDIV4[NFCFRAC] + 1
SIM_CLKDIV4[NFCDIV] + 1
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
38
Preliminary
Freescale Semiconductor, Inc.