K61P144M120SF3 Datasheet, PDF (67/82 Pages) Freescale Semiconductor, Inc – K61 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 46. Master mode DSPI timing (full voltage range) (continued)
Num
DS1
DS2
DS3
Description
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
DS4
DSPI_SCK to DSPI_PCSn invalid delay
DS5
DSPI_SCK to DSPI_SOUT valid
DS6
DSPI_SCK to DSPI_SOUT invalid
DS7
DSPI_SIN to DSPI_SCK input setup
DS8
DSPI_SCK to DSPI_SIN input hold
Min.
4 x t_BUS
(t_SCK/2) - 4
(t_BUS x 2) −
4
(t_BUS x 2) −
4
—
-4.5
20.5
0
Max.
—
(t_SCK/2) + 4
—
—
10
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes
2
3
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
DS3
DS2
DS1
DS4
DS7
DS8
First data
DS5
First data
Data
Last data
DS6
Data
Last data
Num
DS9
DS10
DS11
DS12
DS13
DS14
DS15
Figure 30. DSPI classic SPI timing — master mode
Table 47. Slave mode DSPI timing (full voltage range)
Operating voltage
Description
Frequency of operation
DSPI_SCK input cycle time
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
Min.
1.71
—
8 x t_BUS
(t_SCK/2) - 4
—
0
2
7
—
Max.
3.6
7.5
—
(t_SCK/2) + 4
20
—
—
—
19
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
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