MC9RS08KA8 Datasheet, PDF (7/40 Pages) Freescale Semiconductor, Inc – MCU Block Diagram

Electrical Characteristics
θ_JA = Package thermal resistance, junction-to-ambient, °C /W
P_D = P_int + P_I/O
P_int = I_DD × V_DD, Watts chip internal power
P_I/O = Power dissipation on input and output pins user determined
For most applications, P_I/O << P_int and can be neglected. An approximate relationship between PD and TJ
(if P_I/O is neglected) is:
P_D = K ÷ (T_J + 273°C)
Solving Equation 1 and Equation 2 for K gives:
Eqn. 2
K = P_D × (T_A + 273°C) + θ_JA× (PD)²
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring P_D (at equilibrium)
for a known T_A. Using this value of K, the values of P_D and T_J can be obtained by solving equations 1 and 2 iteratively for any
value of T_A.
3.5 ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions must be used to avoid exposure to static discharge. Qualification tests are performed to ensure that
these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 5. ESD and Latch-up Test Conditions
Model
Human
Body
Machine
Latch-up
Description
Series resistance
Storage capacitance
Number of pulses per pin
Series resistance
Storage capacitance
Number of pulses per pin
Minimum input voltage limit
Maximum input voltage limit
Symbol
R1
C
—
R1
C
—
—
—
Value
1500
100
3
0
200
3
–2.5
7.5
Unit
Ω
pF
—
Ω
pF
—
V
V
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
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