MCF5282UM Datasheet, PDF (625/766 Pages) Freescale Semiconductor, Inc – MCF5282 and MCF5216 ColdFire Microcontroller User s Manual

Debug Support
Table 30-3. BDM/Breakpoint Registers
DRc[4–0]
Register Name
0x00 Configuration/status register
0x01–0x05 Reserved
0x06 Address attribute trigger register
0x07 Trigger definition register
0x08 Program counter breakpoint register
0x09 Program counter breakpoint mask register
0x0A–0x0B Reserved
0x0C Address breakpoint high register
0x0D Address breakpoint low register
0x0E Data breakpoint register
0x0F Data breakpoint mask register
Abbreviation Initial State
Page
CSR
—
AATR
TDR
PBR
PBMR
—
ABHR
ABLR
DBR
DBMR
0x00010_0000 p. 30-10
—
—
0x0000_0005 p. 30-7
0x0000_0000 p. 30-14
—
p. 30-13
—
p. 30-13
—
—
—
p. 30-9
—
p. 30-9
—
p. 30-12
—
p. 30-12
NOTE
Debug control registers can be written by the external development system
or the CPU through the WDEBUG instruction.
CSR is write-only from the programming model. It can be read or written
through the BDM port using the RDMREG and WDMREG commands.
30.4.1 Revision A Shared Debug Resources
In the Revision A implementation of the debug module, certain hardware structures are shared between
BDM and breakpoint functionality as shown in Table 30-4.
Table 30-4. Rev. A Shared BDM/Breakpoint Hardware
Register
BDM Function
AATR
ABHR
DBR
Bus attributes for all memory commands
Address for all memory commands
Data for all BDM write commands
Breakpoint Function
Attributes for address breakpoint
Address for address breakpoint
Data for data breakpoint
Thus, loading a register to perform a specific function that shares hardware resources is destructive to the
shared function. For example, a BDM command to access memory overwrites an address breakpoint in
ABHR. A BDM write command overwrites the data breakpoint in DBR.
30.4.2 Address Attribute Trigger Register (AATR)
The AATR, shown in Figure 30-5, defines address attributes and a mask to be matched in the trigger. The
register value is compared with address attribute signals from the processor’s local high-speed bus, as
defined by the setting of the trigger definition register (TDR).
Freescale Semiconductor
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
30-7