MCF5282UM Datasheet, PDF (326/766 Pages) Freescale Semiconductor, Inc – MCF5282 and MCF5216 ColdFire Microcontroller User s Manual

Fast Ethernet Controller (FEC)
Table 17-12. Programming Examples for MSCR (continued)
Internal FEC Clock
Frequency
50 MHz
66 MHz
MSCR[MII_SPEED]
0xA
0xE
FEC_MDC frequency
2.50 MHz
2.36 MHz
17.4.9 MIB Control Register (MIBC)
The MIBC is a read/write register controlling and observing the state of the MIB block. User software
accesses this register if there is a need to disable the MIB block operation. For example, to clear all MIB
counters in RAM:
1. Disable the MIB block
2. Clear all the MIB RAM locations
3. Enable the MIB block
The MIB_DIS bit is reset to 1. See Table 17-4 for the locations of the MIB counters.
IPSBAR 0x1064
Offset:
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MIB_
MIB_ _IDLE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DIS
W
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 17-9. MIB Control Register (MIBC)
Table 17-13. MIBC Field Descriptions
Field
Description
31 A read/write control bit. If set, the MIB logic halts and not update any MIB counters.
MIB_DIS
30 A read-only status bit. If set the MIB block is not currently updating any MIB counters.
MIB_IDLE
29–0 Reserved.
17.4.10 Receive Control Register (RCR)
RCR controls the operational mode of the receive block and must be written only when ECR[ETHER_EN]
is cleared (initialization time).
17-16
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor