MCF5282UM Datasheet, PDF (546/766 Pages) Freescale Semiconductor, Inc – MCF5282 and MCF5216 ColdFire Microcontroller User s Manual

Queued Analog-to-Digital Converter (QADC)
Bit(s)
15
14
13–8
7
6–0
Name
QSTOP
QDBG
—
SUPV
—
Table 28-3. QADCMCR Field Descriptions
Description
Stop enable.
1 Force QADC to idle state.
0 QADC operates normally.
Debug enable.
1 Finish any conversion in progress, then freeze in debug mode
0 QADC operates normally.
Reserved, should be cleared.
Supervisor/unrestricted data space.
1 All QADC registers are accessible in supervisor mode only; user mode accesses
have no effect and result in a cycle termination error.
0 Only QADCMCR and QADCTEST require supervisor mode access; access to all
other QADC registers is unrestricted
Reserved, should be cleared.
28.6.2 QADC Test Register (QADCTEST)
The QADCTEST is a reserved register. Attempts to access this register outside of factory test mode will
result in access privilege violation.
28.6.3 Port Data Registers (PORTQA & PORTQB)
QADC ports QA and QB are accessed through the 8-bit PORTQA and PORTQB.
Port QA signals are referred to as PQA[4:3, 1:0] when used as a bidirectional, 4-bit, input/output port. Port
QA can also be used for analog inputs (AN[56:55, 53:52]), external trigger inputs (ETRIG[2:1]), and
external multiplexer address outputs (MA[1:0]).
Port QB signals are referred to as PQB[3:0] when used as a 4-bit, digital input-only port. Port QB can also
be used for non-multiplexed (AN[3:0]) and multiplexed (ANZ, ANY, ANX, ANW) analog inputs.
PORTQA and PORTQB are not initialized by reset.
7
Field
Reset
R/W:
Address
6
5
4
3
2
1
0
—
PQA4
PQA3
—
PQA1
PQA0
(AN56) (AN55)
(AN53) (AN52)
(ETRIG2) (ETRIG1)
(MA1)
(MA0)
000
See Note
0
See Note
R
R/W
R
R/W
IPSBAR + 0x19_0006
Figure 28-4. QADC Port QA Data Register (PORTQA)
28-8
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor