MSC8251_11 Datasheet, PDF (61/68 Pages) Freescale Semiconductor, Inc – Single-Core Digital Signal Processor

Hardware Design Considerations
3.5.1.4 DDR2 Unused MAPAR Pin Connections
When the MAPAR signals are not used, refer to Table 43 to determine the correct pin connections.
Table 43. Connectivity of MAPAR Pins for DDR2
Signal Name
Pin connection
MAPAR_OUT
NC
MAPAR_IN
NC
Notes: 1. For the signals listed in this table, the initial M stands for M1 or M2 depending on which DDR controller is used for DDR2.
2. For MSC8251 Revision 1 silicon, these pins were connected to GND. For newer revisions of the MSC8251, connecting these
pins to GND increases device power consumption.
3.5.2 HSSI-Related Pins
3.5.2.1 HSSI Port Is Not Used
The signal names in Table 44 and Table 45 are generic names for a RapidIO interface. For actual pin names refer to Table 1.
Table 44. Connectivity of Serial RapidIO Interface Related Pins When the RapidIO Interface Is Not Used
Signal Name
Pin Connection
SR_IMP_CAL_RX
NC
SR_IMP_CAL_TX
NC
SR[1–2]_REF_CLK
SR[1–2]_REF_CLK
SXCVSS
SXCVSS
SR[1–2]_RXD[3–0]
SR[1–2]_RXD[3–0]
SXCVSS
SXCVSS
SR[1–2]_TXD[3–0]
SR[1–2]_TXD[3–0]
SR[1–2]_PLL_AVDD
NC
NC
In use
SR[1–2]_PLL_AGND
SXPVSS
SXCVSS
In use
In use
In use
SXPVDD
SXCVDD
In use
In use
Note: All lanes in the HSSI SerDes should be powered down. Refer to the MSC8251 Reference Manual for details.
3.5.2.2 HSSI Specific Lane Is Not Used
Table 45. Connectivity of HSSI Related Pins When Specific Lane Is Not Used
Signal Name
Pin Connection
SR_IMP_CAL_RX
SR_IMP_CAL_TX
SR[1–2]_REF_CLK
SR[1–2]_REF_CLK
In use
In use
In use
In use
MSC8251 Single-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
61