MSC8251_11 Datasheet, PDF (40/68 Pages) Freescale Semiconductor, Inc – Single-Core Digital Signal Processor

Electrical Characteristics
Table 22 provides the DDR2 differential specifications for the differential signals MDQS/MDQS and MCK/MCK.
Table 22. DDR2 SDRAM Differential Electrical Characteristics
Parameter
Input AC differential cross-point voltage
Output AC differential cross-point voltage
Symbol
V_IXAC
V_OXAC
Min
0.5 × GVDD – 0.175
0.5 × GVDD – 0.125
Max
0.5 × GVDD + 0.175
0.5 × GVDD + 0.125
Unit
V
V
Table 23 provides the DDR3 differential specifications for the differential signals MDQS/MDQS and MCK/MCK.
Table 23. DDR3 SDRAM Differential Electrical Characteristics
Parameter
Input AC differential cross-point voltage
Output AC differential cross-point voltage
Symbol
V_IXAC
V_OXAC
Min
0.5 × GVDD – 0.150
0.5 × GVDD – 0.115
Max
0.5 × GVDD + 0.150
0.5 × GVDD + 0.115
Unit
V
V
2.6.2 HSSI AC Timing Specifications
The following subsections define the AC timing requirements for the SerDes reference clocks, the PCI Express data lines, the
Serial RapidIO data lines, and the SGMII data lines.
2.6.2.1 AC Requirements for SerDes Reference Clock
Table 24 lists AC requirements for the SerDes reference clocks.
Note: Specifications are valid at the recommended operating conditions listed in Table 3.
Table 24. SR[1–2]_REF_CLK and SR[1–2]_REF_CLK Input Clock Requirements
Parameter
SR[1–2]_REF_CLK/ SR[1–2]_REF_CLK
frequency range
SR[1–2]_REF_CLK/SR[1–2]_REF_CLK clock
frequency tolerance
SR[1–2]_REF_CLK/ SR[1–2]_REF_CLK
reference clock duty cycle (measured at 1.6 V)
SR[1–2]_REF_CLK/SR[1–2]_REF_CLK max
deterministic peak-peak jitter at 10^-6 BER
SR[1–2]_REF_CLK/SR[1–2]_REF_CLK total
reference clock jitter at 10^-6 BER (peak-to-peak
jitter at ref_clk input)
SR[1–2]_REF_CLK/ SR[1–2]_REF_CLK
rising/falling edge rate
Differential input high voltage
Differential input low voltage
Rising edge rate (SR[1–2]_REF_CLK) to falling
edge rate (SR[1–2]_REF_CLK) matching
Symbol
t_{CLK_REF}
t_{CLK_TOL}
t_{CLK_DUTY}
t_{CLK_DJ}
t_{CLK_TJ}
t_CLKRR/t_CLKFR
V_IH
V_IL
Rise-Fall
Matching
Min
—
–350
40
—
—
1
200
—
—
Typical
100/125
—
50
—
—
—
—
—
—
Max
—
350
60
42
86
4
—
–200
20
Units
MHz
ppm
%
ps
ps
V/ns
mV
mV
%
Notes
1
—
—
—
2
3
4
4
5, 6
MSC8251 Single-Core Digital Signal Processor Data Sheet, Rev. 6
40
Freescale Semiconductor