MSC8251_11 Datasheet, PDF (47/68 Pages) Freescale Semiconductor, Inc – Single-Core Digital Signal Processor

Electrical Characteristics
2.6.5 Ethernet Timing
This section describes the AC electrical characteristics for the Ethernet interface.
There are programmable delay units (PDU) that should be programmed differently for each interface to meet timing. There is
a general configuration register 4 (GCR4) used to configure the timing. For additional information, see the MSC8251 Reference
Manual.
2.6.5.1 Management Interface Timing
Table 33 lists the timer input Ethernet controller management interface timing specifications shown in Figure 24.
Table 33. Ethernet Controller Management Interface Timing
Characteristics
Symbol
Min
Max
Unit
GE_MDC frequency
f_MDC
—
2.5
MHz
GE_MDC period
t_MDC
400
—
ns
GE_MDC clock pulse width high
t_{MDC_H}
160
—
ns
GE_MDC clock pulse width low
GE_MDC to GE_MDIO delay²
t_{MDC_L}
160
—
ns
t_MDKHDX
10
70
ns
GE_MDIO to GE_MDC rising edge setup time
t_MDDVKH
20
—
ns
GE_MDC rising edge to GE_MDIO hold time
t_MDDXKH
0
—
ns
Notes: 1. Program the GE_MDC frequency (f_MDC) to a maximum value of 2.5 MHz (400 ns period for t_MDC). The value depends on the
source clock and configuration of MIIMCFG[MCS] and UPSMR[MDCP]. For example, for a source clock of 400 MHz to
achieve f_MDC = 2.5 MHz, program MIIMCFG[MCS] = 0x4 and UPSMR[MDCP] = 0. See the MSC8251 Reference Manual for
configuration details.
2. The value depends on the source clock. For example, for a source clock of 267 MHz, the delay is 70 ns. For a source clock of
333 MHz, the delay is 58 ns.
GE_MDC
t_MDC
t_{MDC_H}
t_{MDC_L}
GE_MDIO
(Input)
GE_MDIO
(Output)
t_MDDVKH
t_MDDXKH
t_MDKHDX
Figure 24. MII Management Interface Timing
MSC8251 Single-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
47