33882 Datasheet, PDF (6/27 Pages) Freescale Semiconductor, Inc – Six-Output Low-Side Switch with SPI and Parallel Input Control

PIN CONNECTIONS
Table 2. QFN Pin Function Description
Pin
Pin Name
Formal Name
16
SCLK
Serial Clock
17
CS
Chip Select
18
SO
Serial Output
23
V_DD
Logic Supply Voltage
Definition
The SCLK pin of the control IC is a bit (shift) clock for the SPI port. It transitions one
time per bit transferred when in operation. It is idle between command transfers. It is
50% duty cycle, and has CMOS levels.
This pin is connected to a chip select output of the control IC.This input has an
internal active 25 µA pull-up and requires CMOS logic levels.
This pin is connected to the SPI Serial Data Input pin of the control IC or to the SI pin
of the next device in a daisy chain. This output will remain tri-stated unless the device
is selected by a low CS pin or the MODE pin goes low. The output signal generated
will have CMOS logic levels and the output data will transition on the falling edges of
SCLK. The serial output data provides fault information for each output and is
returned MSB first when the device is addressed.
This pin is connected to the 5.0 V power supply of the system. A decoupling
capacitor is required from V_DD to ground.
33882
6
Analog Integrated Circuit Device Data
Freescale Semiconductor