33882 Datasheet, PDF (11/27 Pages) Freescale Semiconductor, Inc – Six-Output Low-Side Switch with SPI and Parallel Input Control

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V ≤ V_DD ≤ 5.25 V, 9.0 V ≤ V_PWR ≤ 17 V, -40°C ≤ T_A ≤ 125°C unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Rise Time ⁽²⁷⁾
Output Fall Time ⁽²⁷⁾
Output Turn-ON Delay Time ⁽²⁸⁾
Output Turn-OFF Delay Time ⁽²⁹⁾
Output Short Fault Sense Time ⁽³⁰⁾
R_LOAD = < 1.0 V
Output Short Fault Refresh Time ⁽³¹⁾
R_LOAD = < 1.0 V
Output OFF Open Load Sense Time ⁽³²⁾
Output ON Open Load Sense Time ⁽³³⁾
Output Short Fault ON Duty Cycle ⁽³⁴⁾
DIGITAL INTERFACE TIMING
SCLK Clock High Time (SCLK = 3.2 MHz) ⁽³⁵⁾
SCLK Clock Low Time (SCLK = 3.2 MHz) ⁽³⁵⁾
Falling Edge (0.8 V) of CS to Rising Edge (2.0 V) of SCLK
Required Setup Time ⁽³⁵⁾
t_R
1.0
–
10
µs
t_F
1.0
–
10
µs
t _{DLY (ON)}
1.0
–
10
µs
t _{DLY (OFF)}
1.0
–
10
µs
t _SS
µs
25
–
100
t _REF
ms
3.0
4.5
6.0
t _OS(OFF)
25
60
100
µs
t _OS(ON)
3.0
–
12
ms
SC _DC
0.42
–
3.22
%
t _SCLKH
–
t _SCLKL
–
t _LEAD
–
–
141
ns
–
141
ns
ns
–
140
Falling Edge (0.8 V) of SCLK to Rising Edge (2.0 V) of CS
Required Setup Time ⁽³⁵⁾
t _LAG
–
ns
–
50
SI, CS, SCLK Incoming Signal Rise Time ⁽³⁵⁾
SI, CS, SCLK Incoming Signal Fall Time ⁽³⁵⁾
t _RSI
–
t _FSI
–
–
50
ns
–
50
ns
Notes
27. Output Rise and Fall time measured at 10% to 90% and 90% to 10% voltage points respectively across 15 Ω resistive load to a V_BAT
of 15 V, V_PWR = 15 V.
28. Output Turn-ON Delay Time measured from rising edge (3.0 V) V_IN (CS for serial) to 90% V_O using a 15 Ω load to a V_BAT of 15 V,
V_PWR = 15 V.
29. Output Turn-OFF Delay Time measured from falling edge (1.0 V) V_IN (3.0 V rising edge of CS for serial) to 10% V_O using a 15 Ω load
to a V_BAT of 15 V, V_PWR = 15 V.
30. The shorted output is turned ON during t_SS to retry and check if the short has cleared. The shorted output is in current limit during t_SS.
The t_SS is measured from the start of current limit to the end of current limit.
31. The Short Fault Refresh Time is the waiting period between t_SS retry signals. The shorted output is disabled during this refresh time.
The t_REF is measured from the end of current limit to the start of current limit.
32. The t_OS(OFF) is measured from the time the faulted output is turned OFF until the fault bit is available to be loaded into the internal fault
register. To guarantee a fault is reported on SO, the falling edge of CS must occur at least 100 µs after the faulted output is off.
33. The t_OS(ON) is measured from the time the faulted output is turned ON until the fault bit is available to be loaded into the internal fault
register. To guarantee a fault is reported on SO, the falling edge of CS must occur at least 12 ms after the faulted output is ON.
34. Percent Output Short Fault ON Duty Cycle is defined as (t_SS) ÷ (t_REF) x 100. This specification item is provided FYI and is not tested.
35. Parameter is not tested and values suggested are for system design consideration only in preventing the occurrence of double pulsing.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33882
11