MC9S12XS256RMV1 Datasheet, PDF (582/738 Pages) Freescale Semiconductor, Inc – Reference Manual

128 KByte Flash Module (S12XFTMR128K1V1)
19.3.2.13 Flash Reserved1 Register (FRSV1)
This Flash register is reserved for factory testing.
Offset Module Base + 0x000D
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-19. Flash Reserved1 Register (FRSV1)
All bits in the FRSV1 register read 0 and are not writable.
19.3.2.14 Flash ECC Error Results Register (FECCR)
The FECCR registers contain the result of a detected ECC fault for both single bit and double bit faults.
The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits
in the FECCRIX register (see Section 19.3.2.4). Once ECC fault information has been stored, no other
fault information will be recorded until the specific ECC fault flag has been cleared. In the event of
simultaneous ECC faults the priority for fault recording is double bit fault over single bit fault.
Offset Module Base + 0x000E
7
6
5
4
3
2
1
0
R
ECCR[15:8]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-20. Flash ECC Error Results High Register (FECCRHI)
Offset Module Base + 0x000F
7
6
5
4
3
2
1
0
R
ECCR[7:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-21. Flash ECC Error Results Low Register (FECCRLO)
All FECCR bits are readable but not writable.
S12XS Family Reference Manual, Rev. 1.13
582
Freescale Semiconductor