MC9S12XS256RMV1 Datasheet, PDF (493/738 Pages) Freescale Semiconductor, Inc – Reference Manual

Voltage Regulator (S12VREGL3V3V1)
In Shutdown Mode an external supply driving VDD/VSS can replace the voltage regulator.
17.2.4 VDDF — Regulator Output2 (NVM Logic) Pins
Signals VDDF/VSS are the secondary outputs of VREG_3V3 that provide the power supply for the NVM
logic. These signals are connected to device pins to allow external decoupling capacitors (220 nF, X7R
ceramic).
In Shutdown Mode an external supply driving VDDF/VSS can replace the voltage regulator.
17.2.5 VDDPLL, VSSPLL — Regulator Output3 (PLL) Pins
Signals VDDPLL/VSSPLL are the secondary outputs of VREG_3V3 that provide the power supply for
the PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors
(100 nF...220 nF, X7R ceramic).
In Shutdown Mode, an external supply driving VDDPLL/VSSPLL can replace the voltage regulator.
17.2.6 VDDX — Power Input Pin
Signals VDDX/VSS are monitored by VREG_3V3 with the LVR feature.
17.2.7 VREGEN — Optional Regulator Enable Pin
This optional signal is used to shutdown VREG_3V3. In that case, VDD/VSS and VDDPLL/VSSPLL
must be provided externally. Shutdown mode is entered with VREGEN being low. If VREGEN is high,
the VREG_3V3 is either in Full Performance Mode or in Reduced Power Mode.
For the connectivity of VREGEN, see device specification.
NOTE
Switching from FPM or RPM to shutdown of VREG_3V3 and vice versa
is not supported while MCU is powered.
17.2.8 VREG_API — Optional Autonomous Periodical Interrupt Output Pin
This pin provides the signal selected via APIEA if system is set accordingly. See 17.3.2.3, “Autonomous
Periodical Interrupt Control Register (VREGAPICL) and 17.4.8, “Autonomous Periodical Interrupt (API)
for details.
For the connectivity of VREG_API, see device specification.
17.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in VREG_3V3.
If enabled in the system, the VREG_3V3 will abort all read and write accesses to reserved registers within
it’s memory slice. See device level specification for details.
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
493