MC9S12XS256RMV1 Datasheet, PDF (205/738 Pages) Freescale Semiconductor, Inc – Reference Manual

6.3.2.6 Debug Count Register (DBGCNT)
S12X Debug (S12XDBGV3) Module
Address: 0x0026
7
6
5
4
3
2
1
0
R
0
CNT
W
Reset
0
POR
0
—
—
—
—
—
—
—
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-8. Debug Count Register (DBGCNT)
Read: Anytime
Write: Never
Table 6-16. DBGCNT Field Descriptions
Field
Description
6–0
CNT[6:0]
Count Value — The CNT bits [6:0] indicate the number of valid data 64-bit data lines stored in the Trace Buffer.
Table 6-17 shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer.
When the CNT rolls over to zero, the TBF bit in DBGSR is set and incrementing of CNT will continue in end-
trigger or mid-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The
DBGCNT register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus
should a reset occur during a debug session, the DBGCNT register still indicates after the reset, the number of
valid trace buffer entries stored before the reset occurred. The DBGCNT register is not decremented when
reading from the trace buffer.
TBF (DBGSR)
0
0
0
0
1
1
Table 6-17. CNT Decoding Table
CNT[6:0]
0000000
0000001
0000010
0000100
0000110
..
1111100
1111110
0000000
0000010
..
..
1111110
Description
No data valid
32 bits of one line valid
1 line valid
2 lines valid
3 lines valid
..
62 lines valid
63 lines valid
64 lines valid; if using Begin trigger alignment,
ARM bit will be cleared and the tracing session ends.
64 lines valid,
oldest data has been overwritten by most recent data
6.3.2.7 Debug State Control Registers
There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if
transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the
S12XS Family Reference Manual Rev. 1.13
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