MC9S12XS256RMV1 Datasheet, PDF (119/738 Pages) Freescale Semiconductor, Inc – Reference Manual

2.3.71
Port Integration Module (S12XSPIMV1)
Port AD0 Reduced Drive Register 1 (RDR1AD0)
Address 0x0275
Access: User read/write¹
7
R
RDR1AD07
W
6
RDR1AD06
5
RDR1AD05
4
RDR1AD04
3
RDR1AD03
2
RDR1AD02
1
RDR1AD01
0
RDR1AD00
Reset
0
0
0
0
0
0
0
0
1 _{Read: Anytime}
Write: Anytime
Figure 2-69. Port AD0 Reduced Drive Register 1 (RDR1AD0)
Table 2-68. RDR1AD0 Register Field Descriptions
Field
Description
7-0 Port AD0 reduced drive—Select reduced drive for output pin
RDR1AD0 This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
2.3.72 Port AD0 Pull Up Enable Register 0 (PER0AD0)
Address 0x0276
Access: User read/write¹
7
R
PER0AD07
W
6
PER0AD06
5
PER0AD05
4
PER0AD04
3
PER0AD03
2
PER0AD02
1
PER0AD01
0
PER0AD00
Reset
0
0
0
0
0
0
0
0
1 _{Read: Anytime}
Write: Anytime
Figure 2-70. Port AD0 Pull Device Up Register 0 (PER0AD0)
Table 2-69. PER0AD0 Register Field Descriptions
Field
Description
7-0 Port AD0 pull device enable—Enable pull-up device on input pin
PER0AD0 This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
119