K20P81M100SF2 Datasheet, PDF (55/61 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

Pinout
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to www.freescale.com and perform a keyword search for
the drawing’s document number:
If you want the drawing for this package
Then use this document number
80-pin LQFP
98ASS23174W
81-pin MAPBGA
98ASH98051A
y _{8 Pinout}
ar _{8.1 K20 Signal Multiplexing and Pin Assignments}
The following table shows the signals available on each pin and the locations of these
in ^{pins on the devices supported by this document. The Port Control Module is responsible}
for selecting which ALT functionality is available on each pin.
80 Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
QFP
lim ^{1 ADC1_SE4a ADC1_SE4a PTE0}
SPI1_PCS1 UART1_TX SDHC0_D1
2 ADC1_SE5a ADC1_SE5a PTE1
SPI1_SOUT UART1_RX SDHC0_D0
3 ADC1_SE6a ADC1_SE6a PTE2
SPI1_SCK
UART1_CTS_ SDHC0_DCLK
b
e _{4 ADC1_SE7a ADC1_SE7a PTE3}
SPI1_SIN
UART1_RTS_ SDHC0_CMD
b
r _{5 DISABLED}
PTE4
SPI1_PCS0 UART3_TX SDHC0_D3
P ^{6 DISABLED}
PTE5
SPI1_PCS2 UART3_RX SDHC0_D2
ALT6
I2C1_SDA
I2C1_SCL
ALT7
EzPort
7 VDD
VDD
8 VSS
VSS
9 USB0_DP USB0_DP
10 USB0_DM USB0_DM
11 VOUT33
VOUT33
12 VREGIN
VREGIN
13 PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
14 PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
55