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K20P81M100SF2 Datasheet, PDF (52/61 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet | |||
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Peripheral operating requirements and behaviors
Table 41. I2S master mode timing (continued)
Num
Description
Min.
Max.
Unit
S5
I2S_BCLK to I2S_FS output valid
â
15
ns
S6
I2S_BCLK to I2S_FS output invalid
-2.5
â
ns
S7
I2S_BCLK to I2S_TXD valid
â
15
ns
S8
I2S_BCLK to I2S_TXD invalid
-3
â
ns
S9
I2S_RXD/I2S_FS input setup before I2S_BCLK
20
â
ns
S10
I2S_RXD/I2S_FS input hold after I2S_BCLK
0
â
ns
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
S1
S2
S2
S3
S4
S4
S5
S9
S7
ryS6
ina S10
I2S_TXD
I2S_RXD
Num
S7
S8
S9
S10
lim Figure 22. I2S timing â master mode
eTable 42. I2S alave mode timing
r Description
P Operating voltage
Min.
2.7
S8
Max.
Unit
3.6
V
S11
I2S_BCLK cycle time (input)
8 x tSYS
â
ns
S12
I2S_BCLK pulse width high/low (input)
45%
55%
MCLK period
S13
I2S_FS input setup before I2S_BCLK
10
â
ns
S14
I2S_FS input hold after I2S_BCLK
3
â
ns
S15
I2S_BCLK to I2S_TXD/I2S_FS output valid
â
20
ns
S16
I2S_BCLK to I2S_TXD/I2S_FS output invalid
0
â
ns
S17
I2S_RXD setup before I2S_BCLK
10
â
ns
S18
I2S_RXD hold after I2S_BCLK
2
â
ns
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
52
Preliminary
Freescale Semiconductor, Inc.
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