K20P81M100SF2 Datasheet, PDF (51/61 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

Num
SD6
SD7
SD8
Peripheral operating requirements and behaviors
Table 40. SDHC switching specifications (continued)
Symbol Description
Min.
Max.
Unit
t_OD
SDHC output delay (output valid)
-5
6.5
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
t_THL
SDHC input setup time
5
—
ns
t_THL
SDHC input hold time
0
—
ns
SD3
SD2
SD1
SDHC_CLK
SD6
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
SD7
SD8
inary
lim ^{Input SDHC_DAT[3:0]}
Figure 21. SDHC timing
6.8.7 _I²_{S Switching Specifications}
re ^{This section provides the AC timings for the I2S in master (clocks driven) and slave}
modes (clocks input). All timings are given for non-inverted serial clock polarity
P ^{(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,}
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
Table 41. _I²_{S master mode timing}
Num
S1
S2
S3
S4
Description
Operating voltage
I2S_MCLK cycle time
I2S_MCLK pulse width high/low
I2S_BCLK cycle time
I2S_BCLK pulse width high/low
Min.
2.7
2 x t_SYS
45%
5 x t_SYS
45%
Max.
3.6
55%
—
55%
Unit
V
ns
MCLK period
ns
BCLK period
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
51