K20P81M100SF2 Datasheet, PDF (50/61 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 39. Slave Mode DSPI Timing (High-speed mode) (continued)
Num
DS12
DS13
DS14
DS15
DS16
Description
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSIP_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
Min.
Max.
Unit
0
—
ns
2
—
ns
7
—
ns
—
14
ns
—
14
ns
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
DS10
DS15
DS13
First data
DS14
First data
DS12
Data
Data
DS9
ry _DS11
Last data
DS16
ina^{Last data}
Figure 20. DSPI Classic SPI Timing — Slave Mode
lim _{6.8.6 SDHC Specifications}
e ^{The following timing specs are defined at the chip I/O pin and must be translated}
appropriately to arrive at timing specs/constraints for the physical interface.
r_{Table 40. SDHC switching specifications}
P ^Num
Symbol Description
Min.
Max.
Unit
Card input clock
SD1
fpp
Clock frequency (low speed)
0
400
kHz
fpp
Clock frequency (SD\SDIO full speed)
0
25
MHz
fpp
Clock frequency (MMC full speed)
0
20
MHz
f_OD
Clock frequency (identification mode)
0
400
kHz
SD2
t_WL
Clock low time
7
—
ns
SD3
t_WH
Clock high time
7
—
ns
SD4
t_TLH
Clock rise time
—
3
ns
SD5
t_THL
Clock fall time
—
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
50
Preliminary
Freescale Semiconductor, Inc.