K20P81M100SF2 Datasheet, PDF (16/61 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

General
7. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral
clocks disabled.
5.1.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
• All peripheral clocks disabled except FTFL
• LVD disabled, USB regulator disabled
• No GPIOs toggled
• Code execution from flash
inary
Prelim
Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled
The following data was measured under these conditions:
• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
• All peripheral clocks enabled but peripherals are not in active operation
• LVD disabled, USB regulator disabled
• No GPIOs toggled
• Code execution from flash
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
16
Preliminary
Freescale Semiconductor, Inc.