K20P81M100SF2 Datasheet, PDF (14/61 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

General
5.1.4 Power mode transition operating behaviors
In the table below, all specifications except t_POR, assume the following clock
configuration:
• CPU and system clocks = 100MHz
• Bus and FlexBus clocks = 50 MHz
• Flash clock = 25 MHz
Symbol
t_POR
Table 4. Power mode transition operating behaviors
Description
Min.
Max.
Unit
After a POR event, amount of time from the point V_DD
—
300
μs
y ^{reaches 1.8V to execution of the first instruction}
across the operating temperature range of the chip.
r _{RUN → VLLS1 → RUN}
• RUN → VLLS1
—
4.1
μs
a _{• VLLS1 → RUN}
—
123.8
μs
RUN → VLLS2 → RUN
in ^{• RUN → VLLS2}
• VLLS2 → RUN
—
4.1
μs
—
49.3
μs
RUN → VLLS3 → RUN
lim ^{• RUN→VLLS3}
• VLLS3 → RUN
—
4.1
μs
—
49.2
μs
RUN → LLS → RUN
• RUN → LLS
e _{• LLS → RUN}
—
4.1
μs
—
5.9
μs
r _{RUN → STOP → RUN}
P ^{• RUN → STOP}
—
4.1
μs
• STOP → RUN
—
4.2
μs
Notes
1
RUN → VLPS → RUN
• RUN → VLPS
• VLPS → RUN
—
4.1
μs
—
5.8
μs
1. Normal boot (FTFL_OPT[LPBOOT]=1)
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
14
Preliminary
Freescale Semiconductor, Inc.