MC68CK331CAG16 Datasheet, PDF (54/84 Pages) Freescale Semiconductor, Inc – 32-Bit Modular Microcontroller

Freescale Semiconductor, Inc.
QTEST — QSM Test Register
$YFFC02
QTEST is used during factory testing of the QSM. Accesses to QTEST must be made while the MCU
is in test mode.
QILR — QSM Interrupt Levels Register
$YFFC04
15
14
13
11
10
8
7
0
0
0
ILQSPI
ILSCI
QIVR
RESET:
0
0
0
0
0
0
0
0
QILR determines the priority level of interrupts requested by the QSM and the vector used when an in-
terrupt is acknowledged.
ILQSPI — Interrupt Level for QSPI
ILQSPI determines the priority of QSPI interrupts. This field must be given a value between $0 (inter-
rupts disabled) to $7 (highest priority).
ILSCI — Interrupt Level of SCI
ILSCI determines the priority of SCI interrupts. This field must be given a value between $0 (interrupts
disabled) to $7 (highest priority).
If ILQSPI and ILSCI are the same nonzero value, and both submodules simultaneously request inter-
rupt service, QSPI has priority.
QIVR — QSM Interrupt Vector Register
$YFFC05
15
8
7
0
QILR
INTV
RESET:
0
0
0
0
1
1
1
1
QIVR determines which two vector numbers in the exception vector table are to be used for QSM inter-
rupts. The seven MSB of a user-defined vector number ($40–$FF) must be written into the INTV field
during initialization. The value of INTV0 is supplied by the QSM when an interrupt service request is
acknowledged.
During an interrupt-acknowledge cycle, INTV[7:1] are driven on DATA[7:1] IMB lines. DATA0 is negated
for an SCI interrupt and asserted for a QSPI interrupt. Writes to INTV0 have no meaning or effect.
Reads of INTV0 return a value of one.
At reset, QIVR is initialized to $0F, which corresponds to the uninitialized interrupt vector in the excep-
tion table.
5.3.2 Pin Control Registers
The QSM uses nine pins, eight of which form a parallel port (PORTQS) on the MCU. Although these
pins are used by the serial subsystems, any pin can alternately be assigned as general-purpose I/O on
a pin-by-pin basis.
Pins used for general-purpose I/O must not be assigned to the QSPI by register PQSPAR. To avoid
driving incorrect data, the first byte to be output must be written before DDRQS is configured. DDRQS
must then be written to determine the direction of data flow and to output the value contained in register
PORTQS. Subsequent data for output is written to PORTQS.
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