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K10P144M120SF3 Datasheet, PDF (52/75 Pages) Freescale Semiconductor, Inc – K10 Sub-Family Data Sheet | |||
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Peripheral operating requirements and behaviors
6.6.3.2 12-bit DAC operating behaviors
Table 33. 12-bit DAC operating behaviors
Symbol Description
IDDA_DACL Supply current â low-power mode
P
IDDA_DAC Supply current â high-speed mode
HP
tDACLP Full-scale settling time (0x080 to 0xF7F) â
low-power mode
tDACHP Full-scale settling time (0x080 to 0xF7F) â
high-power mode
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) â low-power mode and high-speed
mode
Vdacoutl DAC output voltage range low â high-
speed mode, no load, DAC set to 0x000
Vdacouth DAC output voltage range high â high-
speed mode, no load, DAC set to 0xFFF
INL Integral non-linearity error â high speed
mode
DNL
Differential non-linearity error â VDACR > 2
V
DNL
Differential non-linearity error â VDACR =
VREF_OUT
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA > = 2.4 V
TCO Temperature coefficient offset voltage
TGE Temperature coefficient gain error
Rop Output resistance load = 3 kΩ
SR Slew rate -80hâ F7Fhâ 80h
⢠High power (SPHP)
⢠Low power (SPLP)
Min.
â
â
â
â
â
â
VDACR
â100
â
â
â
â
â
60
â
â
â
1.2
0.05
Typ.
â
â
100
15
0.7
â
â
â
â
â
±0.4
±0.1
3.7
0.000421
â
1.7
0.12
Max.
150
700
200
30
1
100
VDACR
±8
±1
±1
±0.8
±0.6
90
â
â
250
â
â
CT Channel to channel cross talk
BW 3dB bandwidth
⢠High power (SPHP)
⢠Low power (SPLP)
â
â
-80
550
â
â
40
â
â
Unit
μA
μA
μs
μs
μs
mV
mV
LSB
LSB
LSB
%FSR
%FSR
dB
μV/C
%FSR/C
Ω
V/μs
dB
kHz
Notes
1
1
1
2
3
4
5
5
6
1. Settling within ±1 LSB
2. The INL is measured for 0+100mV to VDACRâ100 mV
3. The DNL is measured for 0+100 mV to VDACRâ100 mV
4. The DNL is measured for 0+100mV to VDACRâ100 mV with VDDA > 2.4V
5. Calculated by a best fit curve from VSS+100 mV to VDACRâ100 mV
K10 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
52
Preliminary
Freescale Semiconductor, Inc.
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