K10P144M120SF3 Datasheet, PDF (38/75 Pages) Freescale Semiconductor, Inc – K10 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
tRC
tRP tREH
tIS
data
data
tRR
tCH
data
Figure 15. Read data latch cycle timing in fast mode
6.4.4 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 25. Flexbus limited voltage range switching specifications
Num
FB1
FB2
FB3
FB4
FB5
Description
Operating voltage
Frequency of operation
Clock period
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
Min.
2.7
—
20
—
0.5
8.5
0.5
Max.
3.6
FB_CLK
—
11.5
—
—
—
Unit
V
MHz
ns
ns
ns
ns
ns
Notes
1
1
2
2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 26. Flexbus full voltage range switching specifications
Num
Description
Operating voltage
Frequency of operation
Min.
1.71
—
Max.
3.6
FB_CLK
Unit
V
MHz
Notes
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
38
Preliminary
Freescale Semiconductor, Inc.