K10P144M120SF3 Datasheet, PDF (35/75 Pages) Freescale Semiconductor, Inc – K10 Sub-Family Data Sheet

6.4.3 NFC specifications
Peripheral operating requirements and behaviors
The NAND flash controller (NFC) implements the interface to standard NAND flash
memory devices. This section describes the timing parameters of the NFC.
In the following table:
• T_H is the flash clock high time and
• T_L is flash clock low time,
which are defined as:
T _NFC = T _L + T _H =
T _{input clock}
SCALER
The SCALER value is derived from the fractional divider specified in the SIM's
CLKDIV4 register:
SCALER ⁼
SIM_CLKDIV4[NFCFRAC] + 1
SIM_CLKDIV4[NFCDIV] + 1
In case the reciprocal of SCALER is an integer, the duty cycle of NFC clock is 50%,
means T_H = T_L. In case the reciprocal of SCALER is not an integer:
T _L = (1 + SCALER / 2) x
T _NFC
2
T _H = (1 – SCALER / 2) x
T _NFC
2
For example, if SCALER is 0.2, then T_H = T_L = T_NFC/2.
T_NFC
T_H T_L
However, if SCALER is 0.667, then T_L = 2/3 x T_NFC and T_H = 1/3 x T_NFC.
T_NFC
T_H T_L
NOTE
The reciprocal of SCALER must be a multiple of 0.5. For
example, 1, 1.5, 2, 2.5, etc.
K10 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
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