MC68HC908QY4_10 Datasheet, PDF (47/168 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Input/Output Registers
3.7.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
Address: $003E
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
= Unimplemented
Indeterminate after reset
Figure 3-4. ADC Data Register (ADR)
3.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
Address: $003F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
ADIV2 ADIV1 ADIV0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 3-5. ADC Input Clock Register (ADICLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate
the internal ADC clock. Table 3-2 shows the available clock configurations. The ADC clock frequency
should be set between f_ADIC(MIN) and f_ADIC(MAX). The analog input level should remain stable for the
entire conversion time (maximum = 17 ADC clock cycles).
Table 3-2. ADC Clock Divide Ratio
ADIV2
ADIV1
0
0
0
0
0
1
0
1
1
X
X = don’t care
ADIV0
0
1
0
1
X
ADC Clock Rate
Bus clock ÷ 1
Bus clock ÷ 2
Bus clock ÷ 4
Bus clock ÷ 8
Bus clock ÷ 16
MC68HC908QY/QT Family Data Sheet, Rev. 6
Freescale Semiconductor
47