MC68HC908QY4_10 Datasheet, PDF (107/168 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Reset and System Initialization
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
LVI
INTERNAL RESET
Figure 13-5. Sources of Internal Reset
Table 13-2. Reset Recovery Timing
Reset Recovery Type
POR/LVI
All others
Actual Number of Cycles
4163 (4096 + 64 + 3)
67 (64 + 3)
13.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power on has occurred. The SIM counter counts out 4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4
cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur.
At power on, the following events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables the oscillator to drive BUSCLKX4.
• Internal clocks to the CPU and modules are held inactive for 4096 BUSCLKX4 cycles to allow
stabilization of the oscillator.
• The POR bit of the SIM reset status register (SRSR) is set
See Figure 13-6.
OSC1
PORRST
BUSCLKX4
BUSCLKX2
RST
ADDRESS BUS
4096
CYCLES
32
CYCLES
32
CYCLES
$FFFE
$FFFF
Figure 13-6. POR Recovery
MC68HC908QY/QT Family Data Sheet, Rev. 6
Freescale Semiconductor
107