MC68HC908QY4_10 Datasheet, PDF (117/168 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

SIM Registers
13.8.1 SIM Reset Status Register
The SRSR register contains flags that show the source of the last reset. The status register will
automatically clear after reading SRSR. A power-on reset sets the POR bit and clears all other bits in the
register. All other reset sources set the individual flag bits but do not clear the register. More than one
reset source can be flagged at any time depending on the conditions at the time of the internal or external
reset. For example, the POR and LVI bit can both be set if the power supply has a slow rise time.
Address: $FE01
Bit 7
6
5
4
3
2
1
Bit 0
Read: POR
PIN
COP
ILOP
ILAD MODRST LVI
0
Write:
POR: 1
0
0
0
0
0
0
0
= Unimplemented
Figure 13-19. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (illegal attempt to fetch an opcode from an unimplemented
address)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
MODRST — Monitor Mode Entry Module Reset Bit
1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after
POR while IRQ ≠ V_TST
0 = POR or read of SRSR
LVI — Low Voltage Inhibit Reset Bit
1 = Last reset caused by LVI circuit
0 = POR or read of SRSR
MC68HC908QY/QT Family Data Sheet, Rev. 6
Freescale Semiconductor
117